A 2/3” 9.5 Mpixel CMOS imager with high frame rate and HDR capabilities
Date & Time
Tuesday, November 10, 2020, 4:15 PM - 4:45 PM
Session Type
Technical session
Klaus Weber

Requirements for live sports production in 4K UHD resolution and high dynamic range (HDR) have multiple challenges for the imaging technology. First and foremost, the high pixel count on any given 2/3” imager size reduces the pixel size to a critical level, while allowing for enough sensitivity and dynamic range required for many different shooting conditions. In addition, stretching the requirements even further, we have high-speed cameras fully integrated into the production workflow supporting native 4K UHD resolution as well as support for the different HDR formats used in live production.  An increase in frame rate increases the bandwidth requirements with the same factor and going from single speed to 3X or 6X speed requires clock rates. This increased frame rate further exceeds the capabilities of the typical 2/3” imagers used today. The imager presented in this paper demonstrates an architecture that supports high spatial and high temporal resolution and a high output data rate. The sensor is manufactured in a 110/180 nm CMOS process and supports a pixel rate of 3.6 Gpix/s, which translates to an output data rate of 58 Gb/s. The imager uses 4T-4shared pixels in combination with kTC-noise suppression by Digital Double Sampling (DDS) and one 16-bit ADC for each column of the shared pixels. This translates to 2112 ADC outputs which has to be multiplexed and serialized to 16 parallel outputs in 32 LVDS lanes at 1.8 Gb/s for which sixteen 132:1 multiplexers are needed. To meet the lag performance for demanding live broadcast applications, typically a transfer time of <1 µs is needed. For high frame rate at full resolution, the available time for column settling and A/D conversion makes it impossible to meet this requirement without addressing multiple rows at the same time. To fulfill the transfer time requirements, an innovative row addressing scheme has been developed to toggle between the different rows. This paper will explain the architecture and readout schemes used to realize a 2/3” 9.5Mpixel CMOS imager with 3.6 Gpix/s enabling high frame-rate operation in native 4K UHD resolution and full HDR support.



Technical Depth of Presentation
What Attendees will Benefit Most from this Presentation
Technologists who are intersted in the latest solutions developed for next generation broadcast cameras
Take-Aways from this Presentation
Understading the challenges of UHD high speed image capturing in broadcast applications See a detailed explanation what high frame rate operation in combination with high pixel count means to imaging technology Get an overview of the technical solutions to handle the demading requirements of high speed image caturing in UHD resolution